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Ms. Ramsha Suhail

Assistant Professor

Ms. Ramsha Suhail is currently working as an Assistant Professor at Department of Electrical, Electronics and Communication Engineering. She is presently in the final stages of completing her Ph.D. in VLSI Design at Indira Gandhi Delhi Technical University for Women (IGDTUW). She obtained her M.Tech in VLSI Design from IGDTUW (2021) and her B.Tech in Electronics and Communication Engineering from Jamia Hamdard (2019). She is a Front-End VLSI Design Researcher with over 7+ years of experience in research and scholarly publishing and has contributed over 15+ publications (2 SCIE, 1 ESCI, 2 Book Chapters, 10+ Scopus indexed International/National Conferences) in the field of low power-low voltage digital circuits. She is an active member of IEEE Young Professionals and IEEE Electron Devices Society.

Research Experience & Fellowships

Senior Research Fellow (SRF), April 2024 – August 2025 Junior Research Fellow (JRF), March 2022 – March 2024

Awards and Recognition

  • Best Paper Award at the 3rd International Conference – Women Researchers in Electronics and Computing (WREC 2025), for the paper “Power- and Variability-Aware Optimization and Analysis of ITdomDFF at 45 nm”, held at Dr B. R. Ambedkar NIT, Jalandhar (March 2025).
  • Secured 3rd Position in the Poster Presentation at the workshop “Robust and Reliable VLSI Circuit Design”, organized by IEEE CASS SBC & IIT Roorkee (February-March 2025).
  • Presented an ESCI paper as Speaker at the IEEE CAS Event 2023, hosted by NXP Semiconductors, Noida and organized by IEEE CASS Delhi Chapter (September 2023).
  • Served as the Training and Placement Faculty Coordinator of the ECE Department for three years (May 2022 – May 2025).

Certifications

  • Attended 3-day hands-on workshop on “Robust and Reliable VLSI Circuit Design”, organized by IIT Roorkee, February-March 2025.
  • Attended One-week AICTE ATAL FDP on “Advances in 3D MOSFET Architectures: Paving the Way for Next-Generation Semiconductor Scaling”, January 2025.
  • Attended an ICT-based One-week STC on “Applications of AI in Electronics System Design”, organized by NITTTR Chandigarh, December 2024.
  • Attended several IEEE Electron Devices Society's Professional Development technical sessions, focusing on advanced CMOS technologies and transistor level innovations.

Areas of Interest:

  • Low Power Digital Circuit Design
  • Device Aware Circuit Design
  • Variation Tolerant VLSI Circuits
  • VLSI for IoT and Edge Devices
  • VLSI for Green Computing